pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 144

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
8.2
The PIC32MX internal device Reset signal is SYSRST
and can be generated from multiple Reset sources,
such as POR (Power-on Reset), BOR (Brown-out
Reset), MCLR (Master Clear Reset), WDTO (Watch-
dog Time-out Reset), SWR (Software Reset) and CMR
(Configuration Mismatch Reset). A Reset source sets
a corresponding status bit in the RCON register to indi-
cate the type of Reset (see Register 8-1). A system
Reset is active at first the POR and asserted until
device configuration settings are loaded and the clock
oscillator sources become stable. The system Reset is
then deasserted allowing the CPU to start fetching
code after 8 system clock cycles (SYSCLK) .
8.2.1
A power-on event generates an internal Power-on
Reset pulse when a V
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR pulse. In particular, V
must fall below V
more information on the V
fications, refer to Section 29.0 “Electrical Character-
istics” of this device family data sheet.
8.2.2
Whenever the MCLR pin is driven low, the device asyn-
chronously asserts SYSRST provided the input pulse on
MCLR is longer than a certain minimum width, as spec-
ified in Section 29.0 “Electrical Characteristics” of
this device family data sheet.
MCLR provides a filter to minimize the effects of noise
and to avoid unwanted Reset conditions. The EXTR bit
(RCON<7>) is set to indicate the MCLR Reset.
EXAMPLE 8-1:
DS61143A-page 142
/* The following code illustrates a software Reset */
// assume interrupts are disabled
// assume the DMA controller is suspended
// assume the device is locked
/* perform a system unlock sequence */
// starting critical sequence
SYSKEY = 0xaa996655; //write first unlock key to SYSKEY
SYSKEY = 0x556699aa
/* set SWRST bit to arm reset */
RSWRSTSET = 1;
/* read RSWRST register to trigger reset */
unsigned int dummy;
dummy = RSWRST;
/* prevent any unwanted code execution until reset occurs*/
while(1);
Reset Modes
POWER-ON RESET (POR)
MCLR RESET (EXTR)
POR
before a new POR is initiated. For
DD
SOFTWARE RESET COMMAND SEQUENCE
rise is detected above V
POR
//write second unlock key to SYSKEY
and V
DD
rise rate speci-
Advance Information
POR
DD
.
8.2.3
The PIC32MX CPU core doesn’t provide a specific
RESET “instruction”; however, a hardware Reset can be
performed in software (Software Reset) by executing a
Software Reset command sequence:
• Write the system unlock sequence
• Set bit, SWRST (RSWRST<0>) = 1
• Read RSWRST register – Reset occurs
• Follow with “while(1);” or 4 “NOP” instructions
Writing a ‘1’ to the RSWRST register sets bit SWRST,
arming the Software Reset. The subsequent read of
the RSWRST register triggers the Software Reset,
which should occur on the next clock cycle following
the read operation. To ensure no other user code is
executed before the Reset event occurs, it is recom-
mended that 4 ‘NOP’ instructions or a “while(1);” state-
ment be placed after the READ instruction.
The SWR Status bit (RCON<6>) is set to indicate the
Software Reset.
SOFTWARE RESET (SWR)
© 2007 Microchip Technology Inc.