pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 198

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
EXAMPLE 9-6:
9.6.2
When the interrupt controller is configured in Multi-
Vector mode, the interrupt requests are serviced at the
calculated vector addresses. The interrupt handler
routine must generate a prologue and an epilogue to
properly configure, save and restore all of the core reg-
isters, along with General Purpose Registers. At a
worst case, all of the modifiable General Purpose Reg-
isters must be saved and restored by the prologue and
epilogue. If the interrupt priority is set to receive its own
General Purpose Register set, the prologue and epi-
logue will not need to save or restore any of the modi-
fiable General Purpose Registers, thus providing the
lowest latency.
DS61143A-page 196
// end of interrupt handler code
addu
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
di
lw
mtc0
lw
mtc0
eret
INTERRUPT PROCESSING IN
MULTI-VECTOR MODE
sp, s8, zero
t9, 72(sp)
t8, 68(sp)
t7, 64(sp)
t6, 60(sp)
t5, 56(sp)
t4, 52(sp)
t3, 48(sp)
t2, 44(sp)
t1, 40(sp)
t0, 36(sp)
v1, 32(sp)
v0, 28(sp)
a3, 24(sp)
a2, 20(sp)
a1, 16(sp)
a0, 12(sp)
s8, 8(sp)
k0, 0(sp)
k0, EPC
k0, 4(sp)
k0, Status
SINGLE VECTOR
INTERRUPT HANDLER
EPILOGUE IN ASSEMBLY
CODE
Advance Information
9.6.2.1
When entering the interrupt handler routine, the Inter-
rupt Service Routine (ISR) must first save the current
priority and exception PC counter from Interrupt Priority
bits, IPL (Status<15:10>), and the ErrorEPC register,
respectively, on the stack. If the routine is presented a
new register set, the previous register set’s stack regis-
ter must be copied to the current set’s stack register.
Then, the requested priority may be stored in the IPLx
from
(Cause<15:10>), Exception Level bit, EXL, and Error
Level bit, ERL, in the Status register (Status<1> and
Status<2>) are cleared, and the Master Interrupt
Enable bit (Status<0>) is set. If the interrupt handler is
not presented a new General Purpose Register set,
these resisters will be saved on the stack. (Cause and
Status are CPU registers; refer to Section 2.0 of this
manual for more information.)
EXAMPLE 9-7:
rdpgpr sp, sp
mfc0
mfc0
srl
addiu
sw
mfc0
sw
ins
ins
mtc0
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
addu
// start interrupt handler code here
Requested
k0, Cause
k1, EPC
k0, k0, 0xa
sp, sp, -76
k1, 0(sp)
k1, Status
k1, 4(sp)
k1, k0, 10, 6
k1,zero, 1, 4
k1, Status
s8, 8(sp)
a0, 12(sp)
a1, 16(sp)
a2, 20(sp)
a3, 24(sp)
v0, 28(sp)
v1, 32(sp)
t0, 36(sp)
t1, 40(sp)
t2, 44(sp)
t3, 48(sp)
t4, 52(sp)
t5, 56(sp)
t6, 60(sp)
t7, 64(sp)
t8, 68(sp)
t9, 72(sp)
s8, sp, zero
Multi-Vector Mode Prologue
Interrupt
PROLOGUE WITHOUT A
DEDICATED GENERAL
PURPOSE REGISTER SET
IN ASSEMBLY CODE
© 2007 Microchip Technology Inc.
Priority
bits,
RIPLx