pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 91

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

5.2
A DMA channel will transfer data from a source to a
destination without CPU intervention.
DMA controller configuration resources:
• The DMA Controller and the corresponding DMA
• The source and destination of the transfer are
• The source and destination are further indepen-
• A DMA transfer can be initiated in one of two
• At each event requiring a DMA transfer, a num-
• The channel keeps track of the number of bytes
• The Source and Destination Pointers are read-
• Interrupts are generated when the Source or
• The Source and Destination Pointers are reset:
© 2007 Microchip Technology Inc.
channel have to be enabled using the ON
(DMACON<15>) and the CHEN (DCHxCON<7>)
bits.
programmable using the DCHxSSA and
DCHxDSA registers respectively.
dently configurable using the DCHxSSIZ and
DCHxDSIZ registers.
ways:
- Software can initiate a transfer by setting the
- An interrupt event occurs that matches the
ber of bytes specified by the cell size (DCHxCSIZ)
will be transferred (one or more transactions will
occur).
transferred from the source to destination, using
Source and Destination Pointers (DCHxSPTR
and DCHxDPTR).
only and are updated after every transaction.
Destination pointer is half of the source or desti-
nation size (DCHxSSIZ/2 or DCHxDSIZ/2), or
when the source or destination counter equals the
size of the source or destination. These interrupts
are CHSHIF, CHDHIF and CHSDIF, CHDDIF,
respectively.
- On any device Reset.
- When the DMA is turned off (ON bit
- A block transfer completes (regardless of the
- A pattern match terminates a transfer
- The CABORT (DCHxECON<6>) flag is
- If the channel source address (DCHxSSA) is
channel CFORCE (DCHxECON<7>) bit.
CHSIRQ (DCHxECON<15:8>) interrupt and
SIRQEN = 1 (DCHxECON<4>). The user can
select any interrupt on the device to start a
DMA transfer.
(DMACON<15>) is ‘0’).
state of CHAEN (DCHxCON<4>)).
(regardless of the state of auto-enable
CHAEN (DCHxCON<4>)).
written.
updated, the Source Pointer (DCHxSPTR)
will be reset.
DMA Controller Operation
Advance Information
• Normally, the DMA channel remains enabled until
• When the channel is disabled, further transfers
• A DMA transfer request will be stopped/aborted
• When a channel abort interrupt occurs, the
5.2.1
Event: Any system event that can initiate or abort a
DMA transfer.
Transaction: A single-word transfer (up to 4 bytes),
comprised of read and write operations.
Cell Transfer: The number of bytes transferred when
a DMA channel has a transfer initiated before waiting
for another event (given by the DCHCSIZ register). A
cell transfer comprises one or more transactions.
Block Transfer: Defined as the number of bytes trans-
ferred when a channel is enabled. The number of bytes
is the larger of either DCHxSSIZ or DCHxDSIZ. A block
transfer comprises one or more cell transfers.
- Similarly, updates to the Destination Address
the DMA channel has completed a block transfer
unless the auto-enable feature is turned on
(i.e., CHAEN = 1).
will be prohibited until the channel is re-enabled
(CHEN is set to ‘1’).
by:
- Writing the CABORT bit (DCHxECON<6>).
- Pattern match occurs if pattern match is
- Interrupt event occurs on the device that
- An address error is detected.
- A block transfer completes provided that
Channel Abort Interrupt Flag, CHTAIF,
(DCHxINT<1>) is set. This allows the user to
detect and recover from an aborted DMA transfer.
When a transfer is aborted, any transaction
currently underway will be completed.
(DCHxDSA) will cause the Destination
Pointer (DCHxDPTR) to be reset.
enabled PATEN = 1 (DCHxECON<5>), pro-
vided that channel CHAEN is not set.
matches the CHAIRQ (DCHxECON<23:16>)
interrupt if enabled by AIRQEN
(DCHxECON<3>).
Channel Auto-Enable mode (CHAEN) is not
set.
PIC32MX FAMILY
DMA CONTROLLER
TERMINOLOGY
DS61143A-page 89