s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 103

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
WMOD
Bit
Identifier
RESET Value
Read/Write
Bit Addressing
WMOD.7
WMOD.6
WMOD.5–.4
WMOD.3
WMOD.2
WMOD.1
WMOD.0
NOTE:
RESET sets WMOD.3 to the current input level of the subsystem clock, XT
is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register.
— Watch Timer Mode Register
Enable/Disable Buzzer Output Bit
Bit 6
Output Buzzer Frequency Selection Bits
XT
Enable/Disable Watch Timer Bit
Watch Timer Speed Control Bit
Watch Timer Clock Selection Bit
0
1
0
0
0
1
1
0
1
0
1
0
1
0
1
IN
W
.7
7
0
8
Input Level Control Bit
Disable buzzer (BUZ) signal output
Enable buzzer (BUZ) signal output
Always logic zero
Input level to XT
Input level to XT
Disable watch timer and clear frequency dividing circuits
Enable watch timer
Normal speed; set IRQW to 0.5 seconds
High-speed operation; set IRQW to 3.91 ms
Select main system clock (fx)/128 as the watch timer clock
Select a subsystem clock as the watch timer clock
0
1
0
1
2 kHz buzzer (BUZ) signal output
4 kHz buzzer (BUZ) signal output
8 kHz buzzer (BUZ) signal output
16 kHz buzzer (BUZ) signal output
"0"
W
6
0
8
IN
IN
pin is low; 1-bit read-only addressable for tests
pin is high; 1-bit read-only addressable for tests
W
.5
5
0
8
W
.4
4
0
8
(note)
.3
R
3
1
in
. If the input level is high, WMOD.3
W
.2
WT
2
0
8
W
.1
1
0
8
F89H, F88H
MEMORY MAP
W
.0
0
0
8
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