s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 300

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s3c72m9

Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
TIMERS and TIMER/COUNTERS
TC1B COUNTER REGISTER (TCNT1B)
The 8-bit counter register for timer/counter 1B, TCNT1B, is mapped to RAM addresses FA7H–FA6H. The 8-bit
register is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT1B register
values to logic zero (00H).
Whenever TMOD1B.2 and TMOD1B.3 are enabled, TCNT1B is cleared to logic zero and counting begins. The
TCNT1B register value is incremented each time an incoming clock signal is detected that matches the signal edge
and frequency setting of the TMOD1B register (specifically, TMOD1B.6, TMOD1B.5, and TMOD1B.4).
Each time TCNT1B is incremented, the new value is compared to the reference value stored in the TC1B reference
register, TREF1B. When TCNT1B = TREF1B, an overflow occurs in the TCNT1B register, the interrupt request flag,
IRQT2, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval
has elapsed.
11-52
TCNT1B
TREF1B
Timer Start Instruction
Count
Clock
TOL2
(TMOD1B.3 is set)
0
1
2
Figure 11-9. TC1B Timing Diagram
n-1
IRQT2 Set
n
Reference Value = n
Match
0
1
Interval Time
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
2
n-1
IRQT2 Set
n
Match
0
1
2
3

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