s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 284

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

TIMERS and TIMER/COUNTERS
TIMER/COUNTER 1A COMPONENT SUMMARY
Mode register (TMOD1A)
Reference register (TREF1A)
Counter register (TCNT1A)
Clock selector circuit
8-bit comparator
Output latch (TOL1)
Output enable flag (TOE1)
Interrupt request flag (IRQT1)
Interrupt enable flag (IET1)
11-36
Register
TMOD1A
TCNT1A
TREF1A
Name
TOE1
Reference
Counter
Control
Type
Flag
Controls TC1A enable/disable
(bit 2); clears and resumes
counting operation (bit 3); sets
input clock and the clock
frequency (bits 6–4)
Select 16-bit TC1 or two 8-bit
TC1A and TC1B (bit 7)
Counts clock pulses matching
the TMOD1A frequency setting
Stores reference value for TC1A
interval setting
Controls TC1A output to the
TCLO1 pin
Activates the timer/counter and selects the internal clock frequency or the
external clock source at the TCL1 pin.
Stores the reference value for the desired number of clock pulses between
interrupt requests.
Counts internal clock pulses that are generated based on bit settings in the
mode register and reference register.
Together with the mode register (TMOD1A), lets you select one of four internal
clock frequencies, or the external system clock source.
Determines when to generate an interrupt by comparing the current value of the
counter (TCNT1A) with the reference value previously programmed into the
reference register (TREF1A).
Where a TC1A clock pulse is stored pending output to the serial I/O circuit or to
the TC1A output pin, TCLO1. When the contents of the TCNT1A and TREF1A
registers coincide, the timer/counter interrupt request flag (IRQT1) is set to "1",
the status of TOL1 is inverted, and an interrupt is generated.
Must be set to logic one before the contents of the TOL1 latch can be output to
TCLO1.
Cleared when TC1A operation starts and set to logic one whenever the counter
value and reference value match.
Must be set to logic one before the interrupt requests generated by timer/counter
1A can be processed.
Table 11-12. TC1A Register Overview
Description
Size
8-bit
8-bit
8-bit
1-bit
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
FA0H–FA1H
FA4H–FA5H
FA8H–FA9H
Address
F92H.3
RAM
(TMOD1A.7 is "0")
8-bit write-only;
8-bit write-only
1-bit write-only
(TMOD1A.3 is
8-bit read-only
Addressing
writeable)
also 1-bit
Mode
Value
Reset
FFH
"0"
"0"
"0"