s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 261

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION
Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system
clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select the clock
frequency. The reference register TREF0 stores the value for the number of clock pulses to be generated between
interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the
TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated.
To program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock
frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF0 register. TCNT0 is
incremented each time an internal counter pulse is detected with the reference clock frequency specified by
TMOD0.4–TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag (IRQT0) is set to logic
one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0 is then cleared to 00H and
TC0 continues counting. The interrupt request mechanism for TC0 includes an interrupt enable flag (IET0) and an
interrupt request flag (IRQT0).
TC0 OPERATION SEQUENCE
The general sequence of operations for using TC0 can be summarized as follows:
1. Set TMOD0.2 to "1" to enable TC0.
2. Set TMOD0.6 to "1" to enable the system clock (fxx) input.
3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fxx/2 n ).
4. Load a value to TREF0 to specify the interval between interrupt requests.
5. Set the TC0 interrupt enable flag (IET0) to "1".
6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting.
7. TCNT0 increments with each internal clock pulse.
8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1" and an interrupt request is generated.
9. Output latch (TOL0) logic toggles high or low.
10. TCNT0 is cleared to 00H and counting resumes.
11. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".
11-13