s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 225

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s3c72m9

Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
INTERRUPT FLAGS
There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each interrupt,
the interrupt master enable flag, which enables or disables all interrupt processing.
Interrupt Master Enable Flag (IME)
The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an IRQx flag
is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the IME flag is set
to logic one.
The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions,
regardless of the current value of the enable memory bank flag (EMB).
Interrupt Enable Flags (IEx)
IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request flag is
set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled.
Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed directly
at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag.
NOTES:
1.
2.
3.
4.
IEx refers generically to all interrupt enable flags.
IRQx refers generically to all interrupt request flags.
IEx = 0 is interrupt disable mode.
IEx = 1 is interrupt enable mode.
IME
Address
0
1
FBAH
FBBH
FBCH
FBDH
FBEH
FBFH
FB8H
Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses
IPR.2
Bit 3
IET2
IEK
IE4
IE1
"0"
"0"
"0"
IPR.1
IRQT2
IPR.0
IRQK
Bit 2
IRQ4
IRQ1
"0"
"0"
"0"
Inhibit all interrupts
Enable all interrupts
Effect of Bit Settings
Bit 1
IET1
IET0
IEW
IEB
IES
IE0
IE2
IRQT1
IRQT0
IRQW
IRQB
IRQS
Bit 0
IRQ0
IRQ2
INTERRUPTS
7-13

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