s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 219

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
INTERRUPT PRIORITY REGISTER (IPR)
The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic zero.
Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction.
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or
you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by a
high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any
other interrupt source.
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if an
interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the IME
flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the current
enable memory bank (EMB) value.
NOTE:
FB2H
IPR.2
0
0
0
0
1
1
1
1
When all interrupts are low priority (the lower three bits of the IPR register are logic zero), the interrupt requested
first will have high priority. Therefore, the first-request interrupt cannot be superceded by any other interrupt. If two or
more interrupt requests are received simultaneously, the priority level is determined according to the standard
interrupt priorities in Table 7-3 (the default priority assigned by hardware when the lower three IPR bits = "0"). In this
case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the high-priority
interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is started.
IME
IPR.1
IPR.2
0
0
1
1
0
0
1
1
Table 7-4. Interrupt Priority Register Settings
IPR.1
INTT1 (INTT1A)
Table 7-3. Standard Interrupt Priorities
INTT0, INTT1B
IPR.0
INTB, INT4
Interrupt
0
1
0
1
0
1
0
1
INTS
INTK
INT0
INT1
IPR.0
Process all interrupt requests at low priority
Process INTB and INT4 interrupts only
Process INT0 interrupts only
Process INT1 interrupts only
Process INTS interrupts only
Process INTT0 and INTT1B interrupts only
Process INTT1 (INTT1A) interrupts only
Process INTK interrupts only
Default Priority
1
2
3
4
5
6
7
Result of IPR Bit Setting
(note)
INTERRUPTS
7-7