s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 194

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

SAM47 INSTRUCTION SET
VENT —
VENTn
Operation:
Description:
5-90
dst
The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable register
bank flag (ERB) into the respective vector addresses. It then points the interrupt service routine to
the corresponding branching locations. The program counter is loaded automatically with the
respective vector addresses which indicate the starting address of the respective vector interrupt
service routines.
The EMB and ERB flags should be modified using VENT before the vector interrupts are
acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous
routine are automatically pushed onto the stack and then popped back when the routine is
completed.
After the return from interrupt (IRET) you do not need to set the EMB and ERB values again.
Instead, use BITR and BITS to clear these values in your program routine.
The starting addresses for vector interrupts and reset operations are pointed to by the VENTn
instruction. These addresses must be stored in ROM locations 0000H–3FFFH. Generally, the
VENTn instructions are coded starting at location 0000H.
The format for VENT instructions is as follows:
EMB
ERB
PC
n = device-specific module address code (n = 0–7)
Load EMB, ERB, and Vector Address
EMB (0,1)
ERB (0,1)
EMB (0,1)
Operand
ERB (0,1)
Operand
ADR
ADR
ADDR (address to branch)
VENTn
d2 ("0" or "1")
d1 ("0" or "1")
Load enable memory bank flag (EMB) and the enable
register bank flag (ERB) and program counter to vector
address, then branch to the corresponding location.
a7
M
E
B
d1,d2,ADDR
a6
E
R
B
a13
a5
Binary Code
Operation Summary
a12
a4
a11 a10
a3
a2
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
a9
a1
a8
a0
ROM (2 x n) 7–6
ROM (2 x n) 5–4
PC12
ROM (2 x n) 3–0
ROM (2 x n + 1) 7–0
(n = 0, 1, 2, 3, 4, 5, 6, 7)
Operation Notation
Bytes
2
PC12–8
EMB, ERB
0, PC13,
Cycles
PC7–0
2