s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 230

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

POWER-DOWN
NOTE:
8-2
System clock status
Clock oscillator
Basic timer
Serial I/O interface
Timer/counter 0
Timer/counter 1
(Timer/counter 1A)
Timer/counter 1B
Watch timer
LCD controller
External interrupts
CPU
Mode release signal
Operation
When the main clock is selected as the system clock (CPU clock).
Table 8-1. Hardware Operation During Power-Down Modes
Can be changed only if the main system
clock is used
Main system clock oscillation stops
Basic timer stops
Operates only if external SCK input is
selected as the serial I/O clock
Operates only if TCL0 is selected as the
counter clock
Operates only if TCL1 is selected as the
counter clock
Operates only if TCL2 is selected as the
counter clock
Operates only if subsystem clock (fxt) is
selected as the counter clock
Operates only if a subsystem clock is se-
lected as LCDCK
INT0, INT1, INT2, INT4, and INTK are
acknowledged
All CPU operations are disabled
Interrupt request signals are enabled by
an interrupt enable flag or by RESET input
Stop Mode (STOP)
(note)
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Can be changed if the main system clock
or subsystem clock is used
CPU clock oscillation stops (main and
subsystem clock oscillation continues)
Basic timer operates (with IRQB set at
each reference interval)
Operates if a clock other than the CPU
clock is selected as the serial I/O clock
Timer/counter 0 operates
Timer/counter 1 (Timer/counter 1A )
operates
Timer/counter 1B operates
Watch timer operates
LCD controller operates
INT0, INT1, INT2, INT4, and INTK are
acknowledged
All CPU operations are disabled
Interrupt request signals are enabled by
an interrupt enable flag or by RESET input
Idle Mode (IDLE)