s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 167

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
LD —
LD
Examples:
Load
(Continued)
2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two
LD RR,#imm Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a
LD A,@RRa
times in succession, only the first LD is executed; the next instructions are treated as NOPs.
Here are two examples of this 'redundancy effect':
The following table contains descriptions of special characteristics of the LD instruction when
used in different addressing modes:
LD Ra,#im
LD A,#im
Instruction
LD A,DA
LD DA,A
LD A,Ra
LD Ra,A
LD
LD
LD
LD
LD
LD
LD
LD
LD
A,#1H
EA,#2H
A,#3H
23H,A
HL,#10H
HL,#20H
A,#3H
EA,#35
@HL,A
Since the 'redundancy effect' occurs with instructions like LD EA,#imm, if this
instruction is used consecutively, the second and additional instructions of the
same type will be treated like NOPs.
Load the data memory contents pointed to by 8-bit RRa register pairs (HL, WX,
WL) to the A register.
Load direct data memory contents to the A register.
Load 4-bit register Ra (E, L, H, X, W, Z, Y) to the A register.
Load 4-bit immediate data into the Ra register (E, L, H, X, W, Y, Z).
redundancy effect if the operation addresses the HL or EA registers.
Load contents of register A to direct data memory address.
Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y).
Operation Description and Guidelines
; A
; NOP
; NOP
; (23H)
; HL
; NOP
; A
; NOP
; (10H)
1H
3H
10H
1H
3H
SAM47 INSTRUCTION SET
5-63