s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 170

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

SAM47 INSTRUCTION SET
LDB —
LDB
Examples:
5-66
(Continued)
1.
2.
3.
4.
5. The P1 address is FF1H and L = 9H (1001B). The address (memb.7–2) is 111100B and (L.3–
6.
Load Bit
Port pin names used in examples 4 and 5 may vary with different SAM47 devices.
2) is 10B. The resulting address, 11110010B specifies P2. The bit value (L.1–0) is specified
as 01B (bit 1). Therefore, P1.@L = P2.1.
The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction
clears the carry flag to logic zero.
LDB
The P1 address is FF1H and the L register contains the value 9H (1001B). The address
(memb.7–2) is 111100B and (L.3–2) is 10B. The resulting address is 11110010B or FF2H
and P2 is addressed. The bit value (L.1–0) is specified as 01B (bit 1).
LD
LDB
The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for
FLAG(3–0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value
is 3. Therefore, @H+FLAG = 20H.3.
FLAG
LD
LDB
The following instruction sequence sets the carry flag and the loads the "1" data value to the
output pin P2.0, setting it to output mode:
SCF
LDB
SCF
LD
LDB
In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit
value is 3, @H+FLAG = 20H.3:
FLAG
RCF
LD
LDB
C,P1.0
L,#9H
C,P1.@L
EQU 20H.3
H,#2H
C,@H+FLAG
P2.0,C
L,#9H
P1.@L,C
EQU 20H.3
H,#2H
@H+FLAG,C
NOTE
; P1.@L specifies P2.1 and C
; C
; C
; P2.0
; C
; P1.@L specifies P2.1
; P2.1
; C
; FLAG(20H.3)
FLAG (20H.3)
"0"
"1"
"1"
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
"1"
"1"
"0"
P2.1