s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 256

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

TIMERS and TIMER/COUNTERS
WATCHDOG TIMER MODE REGISTER (WDMOD)
The watchdog timer mode register, WDMOD, is a 8-bit write-only register. WDMOD register controls to enable or
disable the watchdog function. WDMOD values are set to logic “A5H” following
watchdog timer. Watchdog timer is set to the longest interval because BT overflow signal is generated with the
longest interval.
WATCHDOG TIMER COUNTER (WDCNT)
The watchdog timer counter, WDCNT, is a 3-bit counter. WDCNT is automatically cleared to logic zero, and restarts
whenever the WDTCF register control bit is set to “1”.
also.
WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is
generated. When WDCNT has incremented to hexadecimal ‘07H’, it is cleared to ‘00H’ and an overflow is generated.
The overflow causes the system
counting incoming clock signals.
WATCHDOG TIMER COUNTER CLEAR FLAG (WDTCF)
The watchdog timer counter clear flag, WDTCF, is a 1-bit write instruction. When WDTCF is set to one, it clears the
WDCNT to zero and restarts the WDCNT. WDTCF register bits 2–0 are always logic zero.
NOTES:
1.
2.
11-8
Clock frequencies assume a system oscillator clock frequency (fxx) of 4.19 MHz.
fxx = system clock frequency.
BMOD
x000b
x011b
x101b
x111b
5AH
Any other value
WDMOD
BT Input Clock
fxx/2
fxx/2
fxx/2
fxx/2
RESET
12
9
7
5
Table 11-3. Watchdog Timer Interval Time
Disable watchdog timer function
Enable watchdog timer function
. When the interrupt request is generated, BCNT immediately resumes
WDCNT Input Clock
Watchdog Timer Enable/Disable Control
fxx(2
fxx(2
fxx(2
fxx(2
RESET,
12
9
7
5
2
2
2
2
8
8
8
8
)
)
)
stop, and wait signal clears the WDCNT to logic zero
)
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
WDT Interval Time
2
2
2
2
3
3
3
3
/fxx(2
/fxx(2
/fxx(2
/fxx(2
RESET
12
9
7
5
2
2
2
and this value enables the
2
8
8
8
8
)
)
)
)
218.7-250 ms
54.6-62.5 ms
13.6-15.6 ms
Main Clock
1.75-2 sec