s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 161

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
JPS —
JPS
Operation:
Description:
Example:
Jump (Short)
dst
JPS causes an unconditional branch to the indicated address with the 4-Kbyte program memory
address space. Bits 0–11 of the program counter are replaced with the directly specified address.
The destination address for this jump is specified to the assembler by a label or by an actual
address in program memory.
The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction
JPS
at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS
instruction jumps to the address in the block in which the instruction is located. If the first byte of
the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next
block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or
0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program
malfunction.
Operand
Operand
ADR
ADR
SUB
a7
1
a6
0
a5
0
Jump direct in page (12 bits)
Binary Code
Operation Summary
a4
1
a11 a10
a3
a2
a9
a1
a8
a0
PC14–0
Operation Notation
SAM47 INSTRUCTION SET
PC14–12 + ADR11–0
Bytes
2
Cycles
2
5-57