s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 237

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s3c72m9

Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Output buffers
Output latches
Port mode flags (PM)
Pull-up resistor mode reg (PUMOD1/2)
Count register (BCNT)
Mode register (BMOD)
Mode register (WDMOD)
Counter clear flag (WDTCF)
Count registers (TCNT0/TCNT1A/TCNT1B)
Reference registers (TREF0/TREF1A/TREF1B)
Mode registers (TMOD0/TMOD1A/TMOD1B)
Output enable flags (TOE0/1)
TOL2
Watch timer mode register (WMOD)
LCD contrast control register (LCNST)
LCD mode register (LMOD)
LCD control register (LCON)
Display data memory
Output buffers
SIO mode register (SMOD)
SIO interface buffer (SBUF)
PNE1–PNE3
Comparator mode register (CMOD)
Comparison result register
Timer/Counters 0 and 1:
Hardware Component
LCD Driver/Controller:
Serial I/O Interface:
or Subcomponent
Watch Timer:
Basic Timer:
I/O Ports:
Table 9-1. Hardware Register Values After RESET (Continued)
N-Channel Open-Drain Mode Register
Comparator
If RESET Occurs During
Power-Down Mode
Values retained
Values retained
FFH, FFFFH
Undefined
Undefined
Undefined
A5H
Off
Off
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
If RESET Occurs During
Normal Operation
FFH, FFFFH
Undefined
Undefined
Undefined
Undefined
Undefined
A5H
Off
Off
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
9-3

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