s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 111

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
OPCODE DEFINITIONS
r = Immediate data for register
CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS
A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected
using the PCON register.
In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required
for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of
machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped
— whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB instructions.
The values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows:
Case 1:
Case 2:
Case 3:
NOTE:
Register
Table 5-7. Opcode Definitions (Direct)
REF instructions are skipped in one machine cycle.
WX
EA
HL
YZ
W
A
E
H
Y
L
X
Z
No skip
Skip is 1-byte or 2-byte instruction
Skip is 3-byte instruction
r2
0
0
0
0
1
1
1
1
0
0
1
1
r1
0
0
1
1
0
0
1
1
0
1
0
1
r0
0
1
0
1
0
1
0
1
0
0
0
0
S = 0 cycles
S = 1 cycle
S = 2 cycles
i = Immediate data for indirect addressing
Table 5-8. Opcode Definitions (Indirect)
Register
@WX
@WL
@HL
i2
1
1
1
SAM47 INSTRUCTION SET
i1
0
1
1
i0
1
0
1
5-7