s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 158

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

SAM47 INSTRUCTION SET
INCS —
INCS
Operation:
Description:
Example:
5-54
Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The
instruction sequence
INCS
INCS
INCS
leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Since a
carry occurred, the second instruction is skipped. The carry flag value remains unchanged.
Increment and Skip on Carry
dst
The instruction INCS increments the value of the destination operand by one. An original value of
0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The carry
flag value is unaffected.
Operand
Operand
@HL
@HL
RRb
RRb
DA
DA
R
R
@HL
HL
@HL
Increment register (R); skip on carry
Increment direct data memory; skip on carry
Increment indirect data memory; skip on carry
Increment register pair (RRb); skip on carry
a7
0
1
1
0
1
a6
1
1
1
1
0
a5
0
0
0
1
0
Binary Code
Operation Summary
a4
1
0
1
0
0
; 7EH
; Skip
; 7EH
a3
1
1
1
0
0
a2
r2
r2
0
1
0
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
"1"
a1
r1
r1
"0"
1
0
1
a0
r0
0
1
0
0
R
DA
(HL)
RRb
R + 1; skip on carry
DA + 1; skip on carry
(HL) + 1; skip on carry
Operation Notation
RRb + 1; skip on carry
Bytes
1
2
2
1
Cycles
1 + S
2 + S
2 + S
1 + S