s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 35

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
INTERRUPT STATUS FLAGS (IS0, IS1)
PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags
directly using 1-bit RAM control instructions
By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process
multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit
determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status flags
are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined by the
IPR.
When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically
incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruction,
IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings.
Since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt
processing status. Before interrupt status flags can be addressed, however, you must first execute a DI instruction
to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI instruction to
re-enable interrupt processing.
F
The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:
INTB
Value
IS1
PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing
0
0
1
1
DI
BITR
BITS
EI
Value
IS0
0
1
0
1
IS1
IS0
Status of Currently
Executing Process
Table 2-6. Interrupt Status Flag Bit Settings
0
1
2
–
; Disable interrupt
; IS1
; Allow interrupts according to IPR priority level
; Enable interrupt
All interrupt requests are serviced
Only high-priority interrupt (s) as determined in the interrupt
priority register (IPR) are serviced
No more interrupt requests are serviced
Not applicable; these bit settings are undefined
0
Effect of IS0 and IS1 Settings
on Interrupt Request Control
ADDRESS SPACES
2-19