s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 159

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
IRET —
IRET
Operation:
Description:
Example:
Return from Interrupt
IRET is used at the end of an interrupt service routine. It pops the PC values successively from the
stack and restores them to the program counter. The stack pointer is incremented by six and the
PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also automatically re-
stored to their pre-interrupt values. Program execution continues from the resulting address, which
is generally the instruction immediately after the point at which the interrupt request was detected. If
a lower-level or same-level interrupt was pending when the IRET was executed, IRET will be
executed before the pending interrupt is processed.
Since the 'a14' bit of an interrupt return address is not stored in the stack, this bit location is always
interpreted as a logic zero. The start address in the ROM must for this reason be 3FFFH.
The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location
0122H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively.
The instruction
IRET
leaves the stack pointer with the value 00H and the program returns to continue execution at
location 0123H.
During a return from interrupt, data is popped from the stack to the program counter. The data in
stack locations 0FFH–0FAH is organized as follows:
0FAH
0FBH
0FCH
0FDH
0FEH
0FFH
Operand
Operand
–
–
IS1
C
0
1
PC11 – PC8
SC2
IS0
PC3 – PC0
PC7 – PC4
PC14 – PC12
1
EMB
SC1
0
Binary Code
Operation Summary
Return from interrupt
1
ERB
SC0
0
1
0
1
PC14–8
PC7–0
PSW
SP
SP + 6
Operation Notation
(SP + 4) (SP + 5)
(SP + 2) (SP + 3)
(SP + 1) (SP)
SAM47 INSTRUCTION SET
Bytes
1
Cycles
3
5-55