s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 242

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

I/O PORTS
PULL-UP RESISTOR MODE REGISTER (PUMOD)
The pull-up resistor mode registers (PUMOD1 and PUMOD2) are used to assign internal pull-up resistors by
software to specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is
automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.
PUMOD1 and PUMOD2 are addressable by 8-bit write instructions only. RESET clears PUMOD register values to
logic zero, automatically disconnecting all software-assignable port pull-up resistors.
NOTE:
F
P6 and P7 enable pull-up resistors.
N-CHANNEL OPEN-DRAIN MODE REGISTER (PNE)
The n-channel, open-drain mode register (PNE) is used to configure ports 0, 2, 3,4, 6–13 to n-channel, open-drain or
as push-pull outputs. When a bit in the PNE register is set to "1", the corresponding output pin is configured to n-
channel, open-drain; when set to "0", the output pin is configured to push-pull. The all PNE registers consist of 8-bit
registers only.
10-4
PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
PUMOD ID
PNE ID
PUMOD1
PUMOD2
PNE1
PNE2
PNE3
When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2,
and so on.
BITS
SMB
LD
Table 10-4. Pull-Up Resistor Mode Register (PUMOD) Organization
Address
FDAH
FDBH
FD6H
FD7H
FD8H
FD9H
EMB
15
EA,#0C0H
LD
Address
FDCH
FDDH
FDEH
FDFH
Port 13
Port 9
Bit 3
P0.3
P2.3
P3.3
0
PUR11
PUR3
PUR7
Bit 3
"0"
PUMOD1,EA
Port 12
Port 8
Bit 2
P0.2
P2.2
P3.2
P4.2
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
PUR10
PUR2
PUR6
Bit 2
"0"
;
P6 and P7 enable
Port 11
Port 7
Bit 1
P0.1
P2.1
P3.1
P4.1
PUR13
PUR1
PUR9
Bit 1
"0"
Port 10
Port 6
PUR12
Bit 0
PUR0
PUR4
PUR8
P0.0
P2.0
P3.0
P4.0
Bit 0