s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 253

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
BASIC TIMER MODE REGISTER (BMOD)
The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also 1-
bit addressable. All BMOD values are set to logic zero following
to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following effects:
— Restart the basic timer;
— Control the frequency of clock signal input to the basic timer;
— Determine time interval required for clock oscillation to stabilize following the release of stop mode by an
By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency
during program execution. Four BT frequencies, ranging from fxx/2
value is logic zero, the default clock frequency setting is fxx/2
The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set to
logic one by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt request flag
(IRQB) are both cleared to logic zero, and timer operation restarts.
The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 — determine the
clock input frequency and oscillation stabilization interval.
NOTES:
1.
2.
3.
4.
BMOD.2
interrupt.
Clock frequencies and oscillation stabilization assume a system oscillator clock frequency (fxx) of 4.19 MHz.
fxx = system clock frequency.
Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. The
data in the table column 'Oscillation Stabilization' can also be interpreted as "Interrupt Interval Time".
The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
0
0
1
1
BMOD.1
0
1
0
1
Table 11-2. Basic Timer Mode Register (BMOD) Organization
BMOD.3
BMOD.0
1
0
1
1
1
Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
Basic Timer Input Clock
fxx/2
fxx/2
fxx/2
fxx/2
12
9
7
5
(8.18 kHz)
(32.7 kHz)
(131 kHz)
(1.02 kHz)
12
.
RESET
Basic Timer Start Control Bit
12
to fxx/2
and interrupt request signal generation is set
5
, are selectable. Since BMOD's reset
(Wait time when STOP mode
Interrupt Interval Time
TIMERS and TIMER/COUNTERS
2
2
2
2
17
15
13
20
is released)
/fxx (31.3 ms)
/fxx (7.82 ms)
/fxx (1.95 ms)
/fxx (250 ms)
11-5