s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 220

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

INTERRUPTS
F
The following instruction sequence sets the INT1 interrupt to high priority:
EXTERNAL INTERRUPT 0, 1 AND 2 MODE REGISTERS (IMOD0, IMOD1 AND IMOD2)
The following components are used to process external interrupts at the INT0, INT1 and INT2 pins:
— Edge detection circuit
— Three mode registers, IMOD0, IMOD1 and IMOD2
The mode registers are used to control the triggering edge of the input signal. IMOD0, IMOD1 and IMOD2 settings let
you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The INT4 interrupt
is an exception since its input signal generates an interrupt request on both rising and falling edges. Since INT2 is a
qusi-interrupt, the interrupt request flag (IRQ2) must be cleared by software.
IMOD0, IMOD1 and IMOD2 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic zero,
selecting rising edges as the trigger for incoming interrupt requests.
7-8
IMOD0
IMOD1
IMOD2
FCFH
FB4H
FB5H
Programming Tip — Setting the INT Interrupt Priority
BITS
SMB
DI
LD
LD
EI
IMOD0.3
"0"
"0"
"0"
0
EMB
15
A,#3H
IPR,A
Table 7-5. IMOD0, 1 and 2 Register Organization
"0"
"0"
"0"
0
0
IMOD0.1
IMOD0.1
"0"
"0"
0
0
1
1
0
; IPR.3 (IME)
; IPR.3 (IME)
IMOD0.0
IMOD1.0
IMOD2.0
IMOD0.0
IMOD1.0
IMOD2.0
0
1
0
1
0
1
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Rising edge detection
Falling edge detection
Both rising and falling edge detection
IRQ0 flag cannot be set to "1"
Rising edge detection
Falling edge detection
Effect of IMOD1 and IMOD2 Settings
0
1
Effect of IMOD0 Settings