s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 315

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Segment/Port Output Selection Bits
NOTE:
LCD Clock Selection Bits
NOTE:
Display Mode Selection Bits
LMOD.7
LMOD.3
LMOD.1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
Segment pins that can be used for normal I/O should be configured to output mode for the SEG function.
LCDCK is supplied only when the watch timer operates. To use the LCD controller, bit 2 in the watch mode
register WMOD should be set to 1.
LMOD.6
0
0
0
0
1
1
1
1
0
LMOD.2
LMOD.0
0
1
0
1
0
1
1
LMOD.5
0
0
1
1
0
0
1
1
0
Table 12-5. LCD Mode Register (LMOD) Organization
LMOD.4
1/8 duty (COM0–COM7)
0
1
0
1
0
1
0
1
0
fxx/2
fxx/2
fxx/2
fxx/2
P6–13; SEG port
P7–13; SEG port, P6; normal I/O port
P8–13; SEG port, P6, 7; normal I/O port
P9–13; SEG port, P6, 7, 8; normal I/O port
P10–13; SEG port, P6–9; normal I/O port
P11–13; SEG port, P6–10; normal I/O port
P12, 13; SEG port, P6–11; normal I/O port
P13; SEG port, P6–12; normal I/O port
P6–13; normal I/O port
5
4
7
6
(1024 Hz)
(2048 Hz)
The state of SEG or normal I/O port
(256 Hz)
(512 Hz)
(SEG79/P6.0 – SEG48/P13.3)
LCD Clock (LCDCK)
All LCD dots off
All LCD dots on
Normal display
Function
1/16 duty (COM0–COM15)
fxx/2
fxx/2
fxx/2
fxx/2
LCD CONTROLLER/DRIVER
5
4
3
6
(1024 Hz)
(2048 Hz)
(4096 Hz)
(512 Hz)
(1/8 duty, 1/16 duty)
Total Number of
Segment
88, 80
84, 76
80, 72
76, 68
72, 64
68, 60
64, 56
60, 52
51, 48
12-7