s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 96

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

MEMORY MAP
SMOD
Bit
Identifier
RESET Value
Read/Write
Bit Addressing
SMOD.7–.5
SMOD.4
SMOD.3
SMOD.2
SMOD.1
SMOD.0
4-42
— Serial I/O Mode Register
Serial I/O Clock Selection and SBUF R/W Status Control Bits
NOTES:
1. All kHz frequency ratings assume a system clock of 4.19 MHz.
2. fxx is the system clock.
Bit 4
Initiate Serial I/O Operation Bit
Enable/Disable SIO Data Shifter and Clock Counter Bit
Serial I/O Transmission Mode Selection Bit
LSB/MSB Transmission Mode Selection Bit
0
0
0
1
1
0
1
0
1
0
1
0
1
W
.7
7
0
8
Always logic zero
Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial trans-
mission. When SIO transmission starts, this bit is cleared by hardware to logic
zero
Disable the data shifter and clock counter; the contents of IRQS flag is retained
when serial transmission is completed
Enable the data shifter and clock counter; The IRQS flag is set to logic one when
serial transmission is completed
Receive-only mode
Transmit-and-receive mode
Transmit the most significant bit (MSB) first
Transmit the least significant bit (LSB) first
0
0
1
0
1
0
1
x
0
1
W
.6
6
0
8
Use an external clock at the SCK pin;
Enable SBUF when SIO operation is halted or when SCK goes high
Use the TOL1 clock from timer/counter 1;
Enable SBUF when SIO operation is halted or when SCK goes high
Use the selected CPU clock (fx/4, fx/8, fx/64, or fxt/4) then, enable
SBUF read/write operation. 'x' means 'don't care.'
4.09 kHz clock (fxx/2
262 kHz clock (fxx/2
frequency if you have selected a CPU clock of fx/64
W
.5
5
0
8
"0"
W
4
0
8
4
10
); Note: You cannot select a fx/2
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
)
1/8
W
.3
3
0
W
SIO
.2
2
0
8
W
.1
1
0
8
4
clock
FE1H, FE0H
W
.0
0
0
8