s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 298

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

TIMERS and TIMER/COUNTERS
TC1B MODE REGISTER (TMOD1B)
TMOD1B is the 8-bit mode register for timer/counter 1B. It is addressable by 8-bit write instructions. The TMOD1B.3
bit is also 1-bit write addressable. RESET clears all TMOD1B bits to logic zero. Following a RESET, timer/counter
1B is disabled.
TMOD1B.2 is the enable/disable bit for timer/counter 1. When TMOD1B.3 is set to "1", the contents of TCNT1B,
IRQT2, and TOL2 are cleared, counting starts from 00H, and TMOD1B.3 is automatically reset to "0" for normal
TC1B operation. When TC1B operation stops (TMOD1B.2 = "0"), the contents of the TC1B counter register,
TCNT1B, are retained until TC1B is re-enabled.
The TMOD1B.6, TMOD1B.5, and TMOD1B.4 bit settings are used together to select the TC1B clock source. This
selection involves a variable:
— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in
11-50
TMOD1B.7
TMOD1B.6
TMOD1B.5
TMOD1B.4
TMOD1B.3
TMOD1B.2
TMOD1B.1
TMOD1B.0
FA2H
FA3H
Bit Name
internal TC1B operations.
TMOD1B.3
"0"
Setting
0,1
0
1
0
1
0
0
Table 11-17. TC1B Mode Register (TMOD1B) Organization
TMOD1B.2
TMOD1B.6
Always logic zero
Specify input clock edge and internal frequency
Clear TCNT1B, IRQT2, and TOL2 and resume counting immedi-
ately (This bit is automatically cleared to logic zero immediately
after counting resumes).
Disable timer/counter 1B; retain TCNT1B contents
Enable timer/counter 1B
Always logic zero
Always logic zero
TMOD1B.5
"0"
Resulting TC1B Function
TMOD1B.4
"0"
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Address
FA3H
FA2H