s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 31

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Push Operations
Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack:
PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number determined
by the type of push operation and then points to the next available stack location.
PUSH Instructions
A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are
referenced by the stack pointer: one for the upper register value and another for the lower register. After the PUSH
has executed, the SP is decremented by two and points to the next available stack location.
CALL Instructions
When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit
stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are
also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to
the number of levels permitted in the stack.
Interrupt Routines
An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the
stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is decremented
by six and points to the next available stack location. During an interrupt sequence, subroutines may be nested up
to the number of levels which are permitted in the stack area.
SP - 2
SP - 1
SP
(After PUSH, S
Lower Register
Upper Register
PUSH
SP - 2)
Figure 2-7. Push-Type Stack Operations
SP - 6
SP - 5
SP - 4
SP - 3
SP - 2
SP - 1
SP
(After CALL or LCALL, SP
0
0
0
CALL, LCALL
PC11 - PC8
PC3 - PC0
PC7 - PC4
0
0
PC14 - PC12
PSW
EMB ERB
0
0
SP - 6)
SP - 6
SP - 5
SP - 4
SP - 3
SP - 2
SP - 1
SP
(When INT is acknowledged,
IS1
C
0
SP
INTERRUPT
PC11 - PC8
SC2
PC3 - PC0
PC7 - PC4
IS0
PC14 - PC12
ADDRESS SPACES
PSW
SP - 6)
EMB ERB
SC1
SC0
2-15