s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 20

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s3c72m9

Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
ADDRESS SPACES
F
3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not
;
;
;
;
In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but VENT5
INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to
occur.
2-4
written by a ORG instruction as in Example 2, a CPU malfunction will occur:
PROGRAMMING TIP — Defining Vectored Interrupts (Continued)
ORG
VENT0
VENT1
VENT3
VENT4
VENT5
VENT6
VENT7
ORG
General-purpose ROM area
0000H
1,0,RESET
0,0,INTB
0,0,INT1
0,0,INTS
0,0,INTT0
0,0,INTT1
0,0,INTK
0010H
; EMB
; EMB
; EMB
; EMB
; EMB
; EMB
; EMB
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
0, ERB
0, ERB
0, ERB
1, ERB
0, ERB
0, ERB
0, ERB
0; Jump to INT1 address
0; Jump to INT0 address
0; Jump to INTT0 address
0; Jump to INTT1 address
0; Jump to RESET address
0; Jump to INTB address
0; Jump to INTS address

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