s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 222

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

INTERRUPTS
EXTERNAL KEY INTERRUPT MODE REGISTER (IMODK)
The mode register for external key interrupts at the K0–K7 pins, IMODK, is addressable only by 4-bit write
instructions. RESET clears all IMODK bits to logic zero.
Rising or falling edge can be detected by bit IMODK.2 settings. If a rising or falling edge is detected at any one of the
selected K pin by the IMODK register, the IRQK flag is set to logic one and a release signal for power-down mode is
generated.
NOTES:
1.
2.
7-10
IMODK.2
FB6H
IMODK
To generate a key interrupt, the selected pins must be configured to input mode. If any one pin of the selected pins is
configured to output mode, only falling edge can be detected.
To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select
edge detection and pins by setting IMODK register.
"0"
0
0
1
IMODK.2
Falling edge detection
Rising edge detection
IMODK.2
0, 1
Table 7-6. IMODK Register Bit Settings
IMODK.1
IMODK.1
0
0
1
1
IMODK.0
IMODK.0
0
1
0
1
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Disable key interrupt
Enable edge detection at the K0–K3 pins
Enable edge detection at the K4–K7 pins
Enable edge detection at the K0–K7 pins
Effect of IMODK Settings