s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 304
s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 304 of 382
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TIMERS and TIMER/COUNTERS
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Buzzer Output Frequency Generator
The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the desired
BUZ frequency , load the appropriate value to the WMOD register. This output can then be used to actuate an
external buzzer sound. To generate a BUZ signal, three conditions must be met:
— The WMOD.7 register bit is set to "1"
— The output latch for I/O port 0.3 is cleared to "0"
— The port 0.3 output mode flag (PM0.3) set to 'output' mode
Timing Tests in High-Speed Mode
By setting WMOD.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms.
At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. High-speed
mode is useful for timing events for program debugging sequences.
Check Subsystem Clock Level Feature
The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the
input level at the XT
pin is high; if WMOD.3 is "0", the input level at the XT
pin is low.
IN
IN
11-56
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