LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 115

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Table 4.13
Table 4.14
Mode MAD Pins
Vendor ID
Device ID
Subsystem Vendor ID
Subsystem ID
Mode MAD Pins
Vendor ID
Device ID
Subsystem Vendor ID
Subsystem ID
Subsystem Data Configuration Table for the LSI53C875E (PCI Rev ID 0x26)
Subsystem Data Configuration Table for the LSI53C875 (PCI Rev ID 0x04),
Revision G Only
MAD Bus Programming
MAD[6] Subsystem Data configuration. Refer to
Table 4.14
MAD[5] SCRIPTS RAM disable. Connecting a 4.7 k
between MAD[5] and Vss disables SCRIPTS RAM.
MAD[4] Subsystem Data configuration. Refer to
Table 4.14
MAD[3:1] used to set the size of the external expansion ROM device
attached. Encoding for these pins are listed in
Note:
Offset
Offset
0x2C
0x2E
0x2C
0x2E
0x00
0x02
0x00
0x02
The chip revisions before Revision G of the LSI53C875
(PCI Rev ID 0x04) do not support different Subsystem Data
Configurations. The
Vendor ID (SSVID)
for the different configurations.
for the different configurations.
4-hi, 6-hi
4-hi, 6-hi
Normal
Normal
0x000F
0x000F
0x1000
0x1000
0x1000
0x1000
0x1000
0x1000
Read/Write
Read/Write
4-hi, 6-lo
4-hi, 6-lo
registers are hard wired to zero values.
0x1000
0x000F
0x0000
0x0000
0x1000
0x000F
0x0000
0x0000
Subsystem ID (SSID)
4-low, 6-hi
4-low, 6-hi
Reserved
Reserved
–
–
–
–
–
–
–
–
Table
Table 4.13
Table 4.13
and
4.15.
resistor
4-low, 6-lo
4-low, 6-lo
LSI Logic
LSI Logic
Subsystem
0x000F
0x000F
0x1000
0x0000
0x0000
0x1000
0x0000
0x0000
and
and
4-23