LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 85

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

31
0
0
0
0
0
0
0
Register: 0x2E
Subsystem ID (SSID)
Read Only
SSID
Register: 0x30
Expansion ROM Base Address
Read/Write
ERBA
Configuration Registers
LSI53C875E
LSI53C875
0
15
1
0
0
1
0
0
0
1
0
0
1
0
Subsystem ID
This register supports subsystem identification, which has
a default value of 0x0000 in the LSI53C875 and 0x1000
in the LSI53C875E (see
ming”). To write to this register, connect a 4.7 k
between the MAD[6] pin and V
pin unconnected. The MAD[6] and MAD[4] pins have
internal pull-up resistors and are sensed shortly after the
deassertion of chip reset. In revisions before Revision G
of the LSI53C875, the MAD[6] and MAD[4] pins do not
support the SSID and SSVID configurations, and only
values of 0x0000 can be found in the Subsystem Data
register.
Expansion ROM Base Address
This four-byte register handles the base address and size
information for expansion ROM. It functions exactly like
the
(Memory)
is different. The upper 21 bits correspond to the upper
21 bits of the expansion ROM base address.
0
0
Base Address Zero (I/O)
0
0
0
ERBA
0
0
0
registers, except that the encoding of the bits
0
0
0
0
0
0
0
SSID
0
0
0
0
Section 4.1, “MAD Bus Program-
0
0
0
0
and
ss
0
0
0
and leave the MAD[4]
Base Address One
0
0
0
0
0
0
0
0
0
0
0
resistor
0
0
0
[15:0]
[31:0]
0
3-21
0
0
0
0
0