LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 210

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

6-14
Instruction Set of the I/O Processor
Note:
Note:
None of the signals are set on the SCSI bus in the Target
mode.
None of the signals are cleared on the SCSI bus in the
Target mode.
If reselected, the LSI53C875 fetches the next instruction
from the address pointed to by the 32-bit jump address
field stored in the
Manually set the LSI53C875 to Initiator mode when it is
reselected.
If the CPU sets the SIGP bit in the
(ISTAT)
instruction and fetches the next instruction from the
address pointed to by the 32-bit jump address field stored
in the
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the
(SOCL)
except for testing purposes. When the target bit is set,
the corresponding bit in the
register is also set. When the carry bit is set, the
corresponding bit in the Arithmetic Logic Unit (ALU) is
set.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
trol Latch (SOCL)
except for testing purposes. When the target bit is
cleared, the corresponding bit in the
(SCNTL0)
cleared, the corresponding bit in the ALU is cleared.
Figure 6.3
DMA Next Address (DNAD)
register, the LSI53C875 aborts the Wait Select
register are set. Do not set SACK/ or SATN/
register is cleared. When the carry bit is
illustrates the I/O Instruction register.
DMA Next Address (DNAD)
register. Do not set SACK/ or SATN/
SCSI Output Control Latch
SCSI Control Zero (SCNTL0)
register.
Interrupt Status
SCSI Control Zero
SCSI Output Con-
register.