LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 84

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

3-20
31
x
x
x
x
x
x
x
Register: 0x18
RAM Base Address Two (Memory) SCRIPTS RAM
Read/Write
BAR2
Register: 0x2C
Subsystem Vendor ID (SSVID)
Read Only
SSVID
PCI Functional Description
LSI53C875E
LSI53C875
x
15
1
0
x
1
0
x
x
1
0
x
Base Address Register Two
This register holds the memory base address of the
4 Kbyte internal RAM. Read this register through the
Scratch Register B (SCRATCHB)
register set when bit 3 of the
register is set.
1
0
Subsystem Vendor ID
This register supports subsystem identification, which has
a default value of 0x0000 in the LSI53C875 and 0x1000
in the LSI53C875E (see
ming”). To write to this register, connect a 4.7 k
between the MAD[6] pin and V
pin unconnected. The MAD[6] and MAD[4] pins have
internal pull-up resistors and are sensed shortly after the
deassertion of chip reset. In revisions before Revision G
of the LSI53C875, the MAD[6] and MAD[4] pins do not
support the SSID and SSVID configurations, and only
values of 0x0000 can be found in the Subsystem Data
register.
x
x
0
0
x
BAR2
x
0
0
x
0
0
x
x
SSVID
0
0
x
0
0
x
Section 4.1, “MAD Bus Program-
x
0
0
x
Chip Test Two (CTEST2)
ss
0
0
x
register in the operating
and leave the MAD[4]
x
0
0
x
x
0
0
x
0
0
x
resistor
x
0
0
[31:0]
[15:0]
x
0
0
0
0
0