LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 189

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2. Wait 20 s.
3. Halt the SCSI clock by setting the Halt SCSI Clock bit
4. Set the clock conversion factor using the SCF and CCF fields in the
5. Set the SCLK Doubler Select bit
6. Clear the Halt SCSI Clock bit.
Register: 0x4E (0xCE)
SCSI Test Two (STEST2)
Read/Write
SCE
ROF
DIF
SCE
Three
SCSI Control Three (SCNTL3)
7
0
Note:
(STEST3), bit 5).
ROF
6
0
Do not set this bit during normal operation, since it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
SCSI Control Enable
Setting this bit allows all SCSI control and data lines to
be asserted through the SOCL and
Latch (SODL)
LSI53C875 is configured as a target or initiator.
Reset SCSI Offset
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. Set this bit if a SCSI gross error
condition occurs and to clear the offset when a
synchronous transfer does not complete successfully.
The bit automatically clears itself after resetting the
synchronous offset.
SCSI Differential Mode
Setting this bit allows the LSI53C875 to interface properly
to external differential transceivers. Its only real effect is
to 3-state the SBSY/, SSEL/, and SRST/ pads so that
they can be used as pure inputs. Clearing this bit enables
SE operation. Set this bit in the initialization routine if the
differential pair interface is used.
DIF
5
0
SLB
registers regardless of whether the
4
0
register.
(SCSI Test One
SZM
3
0
AWS
2
0
SCSI Output Data
(STEST1), bit 2).
EXT
1
0
(SCSI Test
LOW
0
0
5-73
7
6
5