LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 305

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Numerics
3.3/5 volt PCI interface
3-state
A
abort operation bit
aborted bit
active negation
active termination
adder register
adder sum output register
always wide SCSI bit
arbitration
assert even SCSI parity bit
assert SATN/ on parity error bit
assert SCSI ACK/ signal bit
assert SCSI ATN/ signal bit
assert SCSI BSY/ signal bit
assert SCSI C_D/ signal bit
assert SCSI data bus bit
assert SCSI I_O signal bits
assert SCSI MSG/ signal bit
assert SCSI REQ/ signal bit
assert SCSI RST/ signal bit
assert SCSI SEL/ signal bit
B
bidirectional
big and little endian support
block move instructions
burst disable bit
burst length bits
burst opcode fetch enable bit
bus fault bit
byte
byte empty in DMA FIFO bit
byte full in DMA FIFO bit
byte offset counter bits
see TolerANT technology
arbitration in progress bit
arbitration mode bits
immediate arbitration bit
in progress bit
lost arbitration bit
mode bits
priority encoder test bit
won arbitration bit
empty in DMA FIFO (FMT)
4-6
5-24
5-24
4-6
5-3
5-53
,
5-40
5-43
,
5-50
2-23
5-27
5-31
5-50
,
5-27
5-74
5-27
5-47
5-39
2-9
6-5
5-3
5-6
5-35
5-53
5-71
5-7
5-21
Index
5-21
,
LSI53C875/875E PCI to Ultra SCSI I/O Processor
5-21
5-21
5-21
5-21
5-7
5-8
2-10
5-21
5-21
5-35
5-27
5-49
5-43
5-34
5-5
C
cache line size enable bit
cache mode, see PCI cache mode
chained block moves
chained mode bit
chip revision level bits
chip test five register
chip test four register
chip test one register
chip test six register
chip test two register
chip test zero register
chip type bits
clear DMA FIFO bit
clear SCSI FIFO bit
clock address incrementor bit
clock byte counter bit
clock conversion factor bits
configuration registers. See PCI configuration registers
configured as I/O bit
configured as memory bit
connected bit
CTEST0 register
CTEST1 register
CTEST2 register
CTEST4 register
CTEST5 register
CTEST6 register
D
data acknowledge status bit
data path
data request status bit
data structure address register
data transfer direction bit
dataRD bit
dataWR bit
DBC register
DBLEN bit 3
DBLSEL bit 2
DCMD register
DCNTL register
destination I/O memory enable bit
DFIFO register
DIEN register
SODL register
SWIDE register
wide SCSI receive bit
wide SCSI send bit
2-16
5-62
5-62
5-72
5-44
5-62
5-7
5-50
5-72
5-45
5-39
5-51
,
5-34
5-35
5-35
5-40
5-42
5-43
5-9
2-36
5-33
2-36
5-37
5-76
5-43
5-36
5-42
5-35
2-34
5-35
5-40
5-42
5-34
5-37
5-37
2-35
5-35
2-36
5-36
5-51
to
5-13
5-37
5-42
2-38
5-31
5-48
3-4
IX-1