LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 72

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

3.2.6 Memory Read Line Command
3-8
transfer at a later time using another bus ownership. If the chip is
transferring multiple cache lines it continues to transfer until the next
cache boundary is reached.
PCI Target Retry – During a Write and Invalidate transfer, if the target
device issues a retry (STOP with no TRDY, indicating that no data was
transferred), the chip relinquishes the bus and immediately tries to finish
the transfer on another bus ownership. The chip issues another Write
and Invalidate command on the next ownership, in accordance with the
PCI specification.
PCI Target Disconnect – During a Write and Invalidate transfer, if the
target device issues a disconnect the LSI53C875 relinquishes the bus
and immediately tries to finish the transfer on another bus ownership.
The chip does not issue another Write and Invalidate command on the
next ownership unless the address is aligned.
This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data
transfers where the memory system and the requesting master might
gain some performance advantage by reading up to a cache line
boundary rather than a single memory cycle. The Read Line function in
the LSI53C875 takes advantage of the PCI 2.1 specification regarding
issuing this command. The functionality of the Enable Read Line bit (bit
3 in
Write and Invalidate mode in terms of conditions that must be met before
a Read Line command is issued. However, the Read Line option
operates exactly like the previous LSI53C8XX chips when cache mode
has been disabled by a CLSE bit reset or when certain conditions exist
in the chip (explained below).
The Read Line mode is enabled by setting bit 3 in the
(DMODE)
issued on every read data transfer, except opcode fetches, as in
previous LSI53C8XX chips.
If cache mode is enabled, a Read Line command is issued on all read
cycles, except opcode fetches, when the following conditions are met:
PCI Functional Description
DMA Mode (DMODE))
register. If cache mode is disabled, Read Line commands are
has been modified to more resemble the
DMA Mode