LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 164

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-48
SIOM
DIOM
SCSI Operating Registers
set in BL[1:0]) during normal operation. The fairness
delay is not inserted during PCI retry cycles. This gives
the CPU and other bus master devices the opportunity to
access the PCI bus between bursts.
1. Only valid if the FIFO size is set to 536 bytes.
Source I/O-Memory Enable
This bit is defined as an I/O Memory Enable bit for the
source address of a Memory Move or Block Move
Command. If this bit is set, then the source address is in
I/O space; and if cleared, then the source address is in
memory space.
This function is useful for register-to-memory operations
using the Memory Move instruction when the LSI53C875
is I/O mapped. Bits 4 and 5 of the
(CTEST2)
configuration status of the LSI53C875.
Destination I/O-Memory Enable
This bit is defined as an I/O Memory Enable bit for the
destination address of a Memory Move or Block Move
Command. If this bit is set, then the destination address
is in I/O space; and if cleared, then the destination
address is in memory space.
This function is useful for memory- to- register operations
using the Memory Move instruction when the LSI53C875
is I/O mapped. Bits 4 and 5 of the
(CTEST2)
configuration status of the LSI53C875.
(CTEST5 Bit 2)
BL2
0
0
0
0
1
1
1
1
register are used to determine the
register are used to determine the
BL1
0
0
1
1
0
0
1
1
BL0
0
1
0
1
0
1
0
1
Burst Length
Transfers
Reserved
Chip Test Two
Chip Test Two
128
32
64
16
2
4
8
1
1
1
5
4