LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 206

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

6-10
Instruction Set of the I/O Processor
1. The LSI53C875 verifies that it is connected to the
2. The LSI53C875 waits for an unserviced phase to
3. The LSI53C875 compares the SCSI phase bits in the
4. If the SCSI phase bits match the value stored in the
Initiator Mode
OPC
0
1
These instructions perform the following steps:
SCSI bus as an Initiator before executing this
instruction.
occur. An unserviced phase is any phase (with SREQ/
asserted) for which the LSI53C875 has not yet
transferred data by responding with a SACK/.
DMA Command (DCMD)
SCSI phase lines stored in the
(SSTAT1)
when SREQ/ is asserted.
SCSI
LSI53C875 transfers the number of bytes specified in
the
address pointed to by the
register. If the opcode bit is cleared and a data
transfer ends on an odd byte boundary, the
LSI53C875 stores the last byte in the
Residue (SWIDE)
or in the
during a send operation. This byte is combined with
the first byte from the subsequent transfer so that a
wide transfer can complete.
DMA Byte Counter (DBC)
Instruction Defined
CHMOV
MOVE
SCSI Status One (SSTAT1)
SCSI Output Control Latch (SOCL)
register. These phase lines are latched
register during a receive operation,
DMA Next Address (DNAD)
register with the latched
register starting at the
SCSI Status One
register, the
SCSI Wide
register