LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 49

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.10 Select/Reselect During Selection/Reselection
2.5.11 Synchronous Operation
In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in the initiator
mode) tries to select a target and is reselected by another. The Select
SCRIPTS instruction has an alternate address to which the SCRIPTS will
jump when this situation occurs. The analogous situation for target
devices is being selected while trying to perform a reselection.
Once a change in operating mode occurs, the initiator SCRIPTS should
start with a Set Initiator instruction or the target SCRIPTS should start
with a Set Target instruction. The Selection and Reselection Enable bits
(SCSI Chip ID (SCID)
so that the LSI53C875 may respond as an initiator or as a target. If only
selection is enabled, the LSI53C875 cannot be reselected as an initiator.
There are also status and interrupt bits in the
(SIST0)
indicating that the LSI53C875 has been selected (bit 5) and reselected
(bit 4).
The LSI53C875 can transfer synchronous SCSI data in both the initiator
and target modes. The
synchronous offset and the transfer period. It may be loaded by the CPU
before SCRIPTS execution begins, from within SCRIPTS using a Table
Indirect I/O instruction, or with a Read-Modify-Write instruction.
The LSI53C875 can receive data from the SCSI bus at a synchronous
transfer period as short as 50 ns, regardless of the transfer period used
to send data. The LSI53C875 can receive data at one-fourth of the
divided SCLK frequency. Depending on the SCLK frequency, the
negotiated transfer period, and the synchronous clock divider, the
LSI53C875 can send synchronous data at intervals as short as 50 ns for
Ultra SCSI, 100 ns for fast SCSI, and 200 ns for SCSI-1.
PCI Cache Mode
and
SCSI Interrupt Enable Zero (SIEN0)
bits 5 and 6, respectively) should both be asserted
SCSI Transfer (SXFER)
SCSI Interrupt Status Zero
register controls both the
registers, respectively,
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