LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 135

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x07 (0x87)
General Purpose (GPREG)
Read/Write
R
GPIO[4:0]
The SDMS Use of GPIO Pins
SDMS software uses GPIO3 to detect a differential board. If the pin is
pulled low externally, the board is configured by SDMS software as a
differential board. If it is pulled high or left floating, SDMS software
configures it as an SE board. The LSI Logic PCI to SCSI host adapters
use the GPIO4 pin in the process of flashing a new SDMS ROM.
SDMS software uses the GPIO0 pin to toggle SCSI device LEDs, turning
on the LED whenever the LSI53C875 is on the SCSI bus. SDMS
7
x
R
x
register. The SCSI ID is defined by the user in a
SCRIPTS select or reselect instruction. The value written
should be the binary-encoded ID value. The priority of the
16 possible IDs, in descending order, is:
Reserved
General Purpose
These bits can be programmed through the
pose Pin Control (GPCNTL)
or to perform special functions. As an output, these pins
can be used to enable or disable external terminators. It
is also possible to program these signals as live inputs
and sense through a SCRIPTS register to register Move
Instruction. GPIO[3:0] default as inputs and GPIO4
defaults as an output pin. When configured as inputs, an
internal pull-up is enabled.
GPIO4 can be used to enable or disable V
power supply to the external flash memory. This bit
powers up with the power to the external memory
disabled.
7
6
5
x
5
Highest
4
3
4
0
2
1
0
x
15
register as inputs, outputs,
14
GPIO
x
13
Lowest
12
11
x
PP
General Pur-
, the 12 V
10
9
0
x
[7:5]
[4:0]
5-19
8