LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 38

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Table 2.2
Table 2.3
2-14
BIt Name
Master Data Parity Error
Master Data Parity Error
Interrupt Enable
Extended Byte Parity
Error Interrupt Enable
(LSI53C875N only)
1. Key:
2. This table only applies when the Enable Parity Checking bit is set.
EPC = Enable Parity Checking (bit 3,
ASEP = Assert SCSI Even Parity (bit 2,
EPC
0
0
1
1
Bits Used for Parity Control and Generation (Cont.)
SCSI Parity Control
AESP
Functional Description
0
1
0
1
Location
DMA Status
(DSTAT), Bit 6
DMA Interrupt
Enable
Bit 6
DMA Interrupt
Enable
Bit 1
Description
Does not check for parity errors. Parity is generated when sending
SCSI data. Asserts odd parity when sending SCSI data.
Does not check for parity errors. Parity is generated when sending
SCSI data. Asserts even parity when sending SCSI data.
Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts odd parity when sending SCSI
data.
Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts even parity when sending SCSI
data.
(DIEN),
(DIEN),
SCSI Control Zero
SCSI Control One
Description
Set when the LSI53C875 as a master detects that a
target device has signaled a parity error during a data
phase.
By clearing this bit, a Master Data Parity Error will not
cause IRQ/ to be asserted, but the status bit will be set
in the
By clearing this bit, an Extended Byte Parity Error will
not cause IRQ/ to be asserted, but the status bit will be
set in the
DMA Status (DSTAT)
DMA Status (DSTAT)
(SCNTL0)).
(SCNTL1)).
register.
register.