LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 145

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x0F (0x8F)
SCSI Status Two (SSTAT2)
Read Only
ILF1
ORF1
OLF1
ILF1
7
0
ORF1
6
0
SIDL Most Significant Byte Full
This bit is set when the most significant byte in the
Input Data Latch (SIDL)
from the SCSI bus to the SCSI Input Data Latch register
before being sent to the DMA FIFO and then to the host
bus. The
SCSI data received asynchronously. Synchronous data
received does not flow through this register.
SODR Most Significant Byte Full
This bit is set when the most significant byte in the SCSI
Output Data Register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR
register is used by the SCSI logic as a second storage
register when sending data synchronously. It is not
accessible to the user. This bit is used to determine how
many bytes reside in the chip when an error occurs.
SODL Most Significant Byte Full
This bit is set when the most significant byte in the
Output Data Latch (SODL)
put Data Latch (SODL)
the DMA logic and the SCSI bus. In synchronous mode,
data is transferred from the host bus to the
Data Latch (SODL)
Data Register (SODR, a hidden buffer register which is
not accessible) before being sent to the SCSI bus. In
asynchronous mode, data is transferred from the host
bus to the
then to the SCSI bus. The SODR buffer register is not
used for asynchronous transfers. It is possible to use this
bit to determine how many bytes reside in the chip when
an error occurs.
OLF1
5
0
SCSI Input Data Latch (SIDL)
SCSI Output Data Latch (SODL)
FF4
4
0
register, and then to the SCSI Output
SPL1
contains data. Data is transferred
register is the interface between
3
x
contains data. The
R
2
x
register contains
LDSC
1
1
SCSI Output
register, and
SCSI Out-
SDP1
SCSI
SCSI
0
x
5-29
7
6
5