LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 142

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-26
Register: 0x0D (0x8D)
SCSI Status Zero (SSTAT0)
Read Only
ILF
ORF
OLF
SCSI Operating Registers
ILF
7
0
ORF
6
0
SIDL Least Significant Byte Full
This bit is set when the least significant byte in the
Input Data Latch (SIDL)
transferred from the SCSI bus to the
Latch (SIDL)
and then to the host bus. The
(SIDL)
asynchronously. Synchronous data received does not
flow through this register.
SODR Least Significant Byte Full
This bit is set when the least significant byte in the SCSI
Output Data Register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR
register is used by the SCSI logic as a second storage
register when sending data synchronously. It is not
readable or writable by the user. It is possible to use this
bit to determine how many bytes reside in the chip when
an error occurs.
SODL Least Significant Byte Full
This bit is set when the least significant byte in the
Output Data Latch (SODL)
put Data Latch (SODL)
the DMA logic and the SCSI bus. In synchronous mode,
data is transferred from the host bus to the
Data Latch (SODL)
Data Register (SODR, a hidden buffer register which is
not accessible) before being sent to the SCSI bus. In
asynchronous mode, data is transferred from the host
bus to the
then to the SCSI bus. The SODR buffer register is not
used for asynchronous transfers. It is possible to use this
bit to determine how many bytes reside in the chip when
an error occurs.
OLF
5
0
register contains SCSI data received
SCSI Output Data Latch (SODL)
register before being sent to the DMA FIFO
AIP
4
0
register, and then to the SCSI Output
LOA
register is the interface between
3
0
register contains data. Data is
contains data. The
SCSI Input Data Latch
WOA
2
0
SCSI Input Data
RST
1
0
SCSI Output
register, and
SCSI Out-
SDP0/
SCSI
SCSI
0
0
7
6
5