LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 141

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

A Block Move instruction is executed with 0x000000
loaded into the
DMA Byte Counter (DBC)
register,
indicating that there are zero bytes to move.
During a Transfer Control instruction, the Compare
Data (bit 18) and Compare Phase (bit 17) bits are set
in the
DMA Byte Counter (DBC)
register while the
LSI53C875 is in target mode.
During a Transfer Control instruction, the Carry Test
bit (bit 21) is set and either the Compare Data (bit 18)
or Compare Phase (bit 17) bit is set.
A Transfer Control instruction is executed with the
reserved bit 22 set.
A Transfer Control instruction is executed with the
Wait for Valid phase bit (bit 16) set while the chip is
in target mode.
A Load/Store instruction is issued with the memory
address mapped to the operating registers of the chip,
not including ROM or RAM.
A Load/Store instruction is issued when the register
address is not aligned with the memory address.
A Load/Store instruction is issued with bit 5 in the
DMA Command (DCMD)
register cleared or bits 3 or
2 set.
A Load/Store instruction when the count value in the
DMA Byte Counter (DBC)
register is not set at 1 to 4.
A Load/Store instruction attempts to cross a Dword
boundary.
A Memory Move instruction is executed with one of
the reserved bits in the
DMA Command (DCMD)
register set.
A Memory Move instruction is executed with the
source and destination addresses not aligned.
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