LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 205

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Block Move Instructions
4. The LSI53C875 transfers the number of bytes
5. If the SATN/ signal is asserted by the Initiator or a
specified in the
starting at the address specified in the
Address (DNAD)
a data transfer ends on an odd byte boundary, the
LSI53C875 stores the last byte in the
Residue (SWIDE)
This byte is combined with the first byte from the
subsequent transfer so that a wide transfer can be
completed.
parity error occurred during the transfer, the transfer
can optionally be halted and an interrupt generated.
The Disable Halt on Parity Error or ATN bit in the
SCSI Control One (SCNTL1)
whether the LSI53C875 halts on these conditions
immediately, or waits until completion of the current
Move.
– If the Vendor Unique Enhancement 1 (VUE1) bit
– If the Vendor Unique Enhancement 1 bit is clear
– If any other Group Code is received, the
overwrites the
with the length of the Command Descriptor Block:
6, 10, or 12 bytes.
(SCSI Control Two (SCNTL2),
LSI53C875 receives the number of bytes in the byte
count regardless of the group code.
and group code is vendor unique, the LSI53C875
receives the number of bytes in the count.
Counter (DBC)
LSI53C875 requests the number of bytes specified
in the
Byte Counter (DBC)
illegal instruction interrupt is generated.
DMA Byte Counter (DBC)
DMA Byte Counter (DBC)
DMA Byte Counter (DBC)
register. If the Opcode bit is set and
register is not modified and the
register during a receive operation.
register contains 0x000000, an
register controls
bit 1) is set, the
register. If the
SCSI Wide
DMA Next
DMA Byte
register
register
DMA
6-9