LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 35

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

location 0x0000 from memory is routed to lane three, and the data at
location 0x0003 is routed to byte lane 0. In little endian mode, the first
byte of an aligned SCSI to PCI transfer is routed to lane zero and
succeeding transfers are routed to ascending lanes. This mode of
operation also applies to the add-in ROM interface. The byte of data
accessed at location 0x0000 from memory is routed to lane zero, and
the data at location 0x0003 is routed to byte lane 3.
The Big_Lit pin gives the LSI53C875 the flexibility of operating with either
big or little endian byte orientation. Internally, in either mode, the actual
byte lanes of the DMA FIFO and registers are not modified. The
LSI53C875 supports slave accesses in big or little endian mode.
When a Dword is accessed, no repositioning of the individual bytes is
necessary since Dwords are addressed by the address of the least
significant byte. SCRIPTS always uses Dwords in 32-bit systems, so
compatibility is maintained between systems using different byte
orientations. When less than a Dword is accessed, individual bytes must
be repositioned. Internally, the LSI53C875 adjusts the byte control logic
of the DMA FIFO and register decodes to access the appropriate byte
lanes. The registers always appear on the same byte lane, but the
address of the register is repositioned.
Big/little endian mode selection has the most effect on individual byte
access. Internally, the LSI53C875 adjusts the byte control logic of the
DMA FIFO and register decodes to enable the appropriate byte lane. The
registers always appear on the same byte lane, but the address of the
register is repositioned.
Data to be transferred between system memory and the SCSI bus
always starts at address zero and continues through address ‘n’ – there
is no byte ordering in the chip. The first byte in from the SCSI bus goes
to address 0, the second to address 1, etc. Going out onto the SCSI bus,
address zero is the first byte out on the SCSI bus, address 1 is the
second byte, etc. The only difference is that in a little endian system,
address 0 is on byte lane 0, and in big endian mode address zero is on
byte lane 3.
Correct SCRIPTS are generated if the SCRIPTS compiler is run on a
system that has the same byte ordering as the target system. Any
SCRIPTS patching in memory must patch the instruction with the byte
ordering that the SCRIPTS processor expects.
PCI Cache Mode
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