LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 188

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5.0.0.1 Doubling the SCSI CLK Frequency
5-72
Register: 0x4D (0xCD)
SCSI Test One (STEST1)
Read/Write
SCLK
SISO
R
DBLEN
DBLSEL
R
The LSI53C875 SCSI clock doubler doubles a 40 MHz SCSI clock,
increasing the frequency to 80 MHz. Follow these steps to use the clock
doubler:
1. Set the SCLK Doubler Enable bit
SCSI Operating Registers
SCLK
7
0
SISO
6
0
SCSI Clock
When set, this bit disables the external SCLK (SCSI
Clock) pin, and the chip uses the PCI clock as the
internal SCSI clock. If a transfer rate of 10 Mbytes/s (or
20 Mbytes/s on a wide SCSI bus) is desired on the SCSI
bus, this bit must be cleared and a 40 MHz external
SCLK must be provided.
SCSI Isolation Mode
This bit allows the LSI53C875 to put the SCSI
bidirectional and input pins into a low power mode when
the SCSI bus is not in use. When this bit is set, the SCSI
bus inputs are logically isolated from the SCSI bus.
Reserved
Doubler Enable
Set this bit to bring the SCSI clock doubler out of the
powered-down state. The default value of this bit is clear
(SCSI clock doubler powered down). Set bit 2 after
setting this bit, to double the SCLK frequency.
Doubler Select
Set this bit after powering up the SCSI clock doubler to
double the SCLK frequency. This bit has no effect unless
bit 3 is set.
Reserved
5
x
R
4
x
DBLEN
(SCSI Test One
3
0
DBLSEL
2
0
(STEST1), bit 3).
1
x
R
0
x
[5:4]
[1:0]
7
6
3
2