LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 216

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

6-20
R
ENDID[3:0]
R
CC
TM
R
ACK
R
ATN
Instruction Set of the I/O Processor
Reserved
Encoded SCSI Destination ID
This 4-bit field specifies the destination SCSI ID for an I/O
instruction.
Reserved
Set/Clear Carry
This bit is used in conjunction with a Set or Clear
instruction to set or clear the Carry bit. Setting this bit with
a Set instruction asserts the Carry bit in the ALU. Clear-
ing this bit with a Clear instruction deasserts the Carry bit
in the ALU.
Set/Clear Target Mode
This bit is used in conjunction with a Set or Clear
instruction to set or clear Target mode. Setting this bit
with a Set instruction configures the LSI53C875 as a
Target device (this sets bit 0 of the
(SCNTL0)
instruction configures the LSI53C875 as an Initiator
device (this clears bit 0 of the SCNTL0 register).
Reserved
Set/Clear SACK/
Reserved
Set/Clear SATN/
These two bits are used in conjunction with a Set or Clear
instruction to assert or deassert the corresponding SCSI
control signal. Bit 6 controls the SCSI SACK/ signal. Bit 3
controls the SCSI SATN/ signal.
Setting either of these bits will set or reset the
corresponding bit in the
(SOCL)
Set instruction is used to assert SACK/ and/or SATN/ on
the SCSI bus. The Clear instruction is used to deassert
SACK/ and/or SATN/ on the SCSI bus.
Since SACK/ and SATN/ are Initiator signals, they are not
asserted on the SCSI bus unless the LSI53C875 is
operating as an Initiator or the SCSI Loopback Enable bit
is set in the
register, depending on the instruction used. The
register). Clearing this bit with a Clear
SCSI Status Two (SSTAT2)
SCSI Output Control Latch
SCSI Control Zero
register.
[23:20]
[19:16]
[15:11]
[8:7]
[5:4]
10
9
6
3