LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 307

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

M
MACNTL register
MAD bus programming
manual start mode bit
master control for set or reset pulses bit
master data parity error bit
master enable bit
master parity error enable bit
max SCSI synchronous offset bits
memory access control register
memory move instructions
memory read line command
memory read multiple command
memory write and invalidate command
MG[7:0]
min_gnt (MG[7:0])
N
no flush memory move instruction
O
opcode fetch bursting
operating registers
MAD[0]
MAD[3:1]
MAD[4]
MAD[5]
MAD[6]
MAD[7]
and SCRIPTS instruction prefetching
no flush option
write and invalidate mode bit
adder sum output
chip test five
chip test four
chip test one
chip test six
chip test three
chip test two
chip test zero
data structure address
DMA byte counter
DMA command
DMA control
DMA FIFO
DMA interrupt enable
DMA mode
DMA next address
DMA SCRIPTS pointer
DMA SCRIPTS pointer save
DMA status
general information
general purpose
general purpose pin control
interrupt status
memory access control
response ID one
response ID zero
scratch byte
scratch register A
scratch register B
SCSI bus control Lines
3-24
4-24
4-23
4-23
4-23
4-22
4-24
5-39
5-47
5-23
5-43
5-51
5-51
5-42
5-35
5-35
5-40
5-62
5-63
5-34
3-24
5-37
2-5
5-31
5-45
5-19
5-70
5-69
5-53
5-47
5-79
2-6
5-49
5-44
5-45
5-1
4-22
5-50
6-33
5-31
5-24
5-46
5-22
5-62
Index
3-8
5-41
,
5-63
5-62
3-9
5-46
3-14
5-50
6-34
5-17
3-6
5-42
2-5
P
package and feature options
parity
parity error bit
PCI cache mode
PCI commands
PCI configuration registers
SCSI bus data lines
SCSI chip ID
SCSI control one register
SCSI control register two
SCSI control three
SCSI control zero
SCSI destination ID
SCSI first byte received
SCSI input data latch
SCSI interrupt enable one
SCSI interrupt enable zero
SCSI interrupt status one
SCSI interrupt status zero
SCSI longitudinal parity
SCSI output control latch
SCSI output data latch
SCSI selector ID
SCSI status one
SCSI status two
SCSI status zero
SCSI test one
SCSI test three
SCSI test two
SCSI test zero
SCSI timer one
SCSI timer zero
SCSI transfer
SCSI wide residue
temporary stack
cache line size enable bit
cache line size register
enable read multiple bit
memory read line command
memory read multiple command
memory write and invalidate command
write and invalidate enable bit
base address one (memory)
base address zero (I/O)
cache line size
class code
command
data
device ID
expansion ROM base address
header type
interrupt line
interrupt pin
latency timer
max_lat
min_gnt
next item pointer
power management control/status
revision ID
status
subsystem data
subsystem ID (SSID)
2-12
write and invalidate mode bit
3-28
3-15
3-24
3-24
3-13
3-13
5-58
3-17
3-17
3-2
3-19
3-23
3-23
3-18
3-4
5-14
5-15
5-73
5-72
5-70
3-18
5-75
5-66
3-20
5-38
5-64
5-29
5-27
5-22
3-25
5-26
5-3
5-12
5-61
5-18
5-78
3-21
5-77
5-78
3-11
3-18
5-60
5-49
5-20
3-19
1-4
5-9
5-21
5-6
5-59
5-51
5-56
5-55
5-53
3-8
to
3-19
5-38
3-21
3-24
3-9
3-14
3-26
3-6
IX-3